In present semiconductor technology, CMOS devices such as nFETs or pFETs are typically fabricated on semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have a higher mobility for a (110) Si surface orientation. That is, hole mobility values on (100) Si are roughly 2×–4×lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETS having larger widths are undesirable since they take up a significant amount of chip area.
In contrast to the foregoing, hole mobilities on (110) Si are 2× higher than on (100) Si; therefore, pFETS formed on a (110) Si surface will exhibit significantly higher drive currents than pFETs formed on a (100) Si surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above discussion, the (110) Si surface is optimal for pFET devices because of the excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Methods have been described to form planar hybrid substrates with different surface orientations through wafer bonding. In such endeavors, the planar hybrid substrate is obtained mainly through semiconductor-to-insulator, or insulator-to-insulator wafer bonding to achieve pFETs and nFETs on their own optimized crystal orientation for high performance device manufacture. However, at least one type of MOSFET (either pFETs or nFETs) is on an SOI material, while the other type of MOSFET is either on a bulk semiconductor or an SOI with a thicker SOI film.
Recently, hybrid crystal oriented substrates have been prepared using a method that includes providing a bonded substrate comprising at least a top semiconductor layer of a first crystallographic orientation and a bottom semiconductor layer of a second crystallographic orientation that differs from the first crystallographic orientation; protecting a portion of the bonded substrate providing a first region, while leaving another portion of the bonded substrate unprotected providing a second region; etching the unprotected portion of the bonded substrate to expose the bottom semiconductor layer; regrowing a semiconductor material on the bottom semiconductor layer such that the semiconductor material has the second crystallographic orientation; and planarizing. Such a technique is described, for example, in U.S. application Ser. No. 10/250,241, Jun. 17, 2003. The '241 application discloses that one of the semiconductor layers may be from a prefabricated SOI substrate. In such a case, the prefabricated SOI wafer is bonded to another wafer that can also include a prefabricated SOI wafer.
Although the above technique is feasible, there is no freedom as to where the buried insulating layer will be present in such instances.
In view of the above, there is a need for providing a method of fabricating a SOI substrate material in which the SOI layer of the SOI material has a different crystal orientation than the underlying Si-containing layer and wherein the buried insulating region is formed after bonding. By forming the buried insulating region after bonding, it is possible to provide a hybrid SOI substrate in which the buried insulating region can exist within different regions of the hybrid SOI substrate. The term “hybrid SOI substrate” denotes a substrate material that includes an upper Si-containing layer and a lower Si-containing layer of different crystallographic orientations, wherein a buried insulating region is located in at least one of the Si-containing layers or through an interface located therebetween.